Template: Pico LCD 1.8 Spec
Overview
Provide Pico C demo.
Specifications
Item | Parameter |
Supply Voltage | 2.6V ~ 5.5V |
Operating Current | 40mA |
Screen | TFT |
Controller | ST7735S |
Communication Interface | 4-wire SPI |
Resolution | 128(H)RGB x 160(V) Pixels |
Pixel Size | 0.219(H)x 0.219(V)mm |
Display Size | 28.03(H)x 35.04(V)mm |
Outline Dimensions | 34.5(H)x 52.00(V) mm |
Pinout
Dimension
LCD & Controller
ST7735S is a 132*162 pixel LCD, and this product is a 128*160 pixel LCD, so some processing is done on the display: the display starts from the second pixel in the horizontal direction and the first pixel in the vertical direction. Start to display, so as to ensure that the position corresponding to the RAM in the LCD is consistent with the actual position when displayed.
The LCD supports 12-bit, 16-bit and 18-bit input color formats per pixel, namely RGB444, RGB565, and RGB666 three color formats, this demo uses RGB565 color format, which is also a commonly used RGB format.
The LCD uses a four-wire SPI communication interface, which can greatly save the GPIO port, and the communication speed will be faster.
Working Protocol
Note: Different from the traditional SPI protocol, the data line from the slave to the master is hidden since the device only has a display requirement.
RESX Is the reset pin, it should be low when powering the module and be higher at other times;;
CSX is slave chip select, when CS is low, the chip is enabled.
D/CX is data/command control pin, when DC = 0, write command, when DC = 1, write data
SDA is the data pin for transmitting RGB data, it works as the MOSI pin of SPI interface;
SCL work s the SCLK pins of SPI interface.
SPI communication has data transfer timing, which is combined by CPHA and CPOL.
CPOL determines the level of the serial synchronous clock at an idle state. When CPOL = 0, the level is Low. However, CPOL has little effect on the transmission.
CPHA determines whether data is collected at the first clock edge or at the second clock edge of the serial synchronous clock; when CPHL = 0, data is collected at the first clock edge.
There are 4 SPI communication modes. SPI0 is commonly used, in which CPHL = 0, CPOL = 0.