Difference between revisions of "Template:Pico e-Paper 5.83 B Spec"
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==Features== | ==Features== | ||
*No backlight keeps displaying last content for a long time even when power down | *No backlight keeps displaying last content for a long time even when power down |
Revision as of 06:02, 18 January 2022
Overview
5.83inch EPD (Electronic Paper Display) Module For Raspberry Pi Pico, 648×480 Pixels, Black / White/ Red, SPI Interface
Features
- No backlight keeps displaying last content for a long time even when power down
- Ultra-low power consumption, basically power is only required for refreshing
- SPI interface requires minimal IO pins
- 2x user buttons and 1x reset button for easy interacting
Specification
- Operating voltage: 3.3V
- Interface:SPI
- Outline dimensions: 125.40mm x 99.50mm x 1.18mm
- Display size: 119.232(H) x 88.320(V)
- Dot pitch: 0.184 x 0.184mm
- Resolution: 648×480 pixels
- Display color: Black, white, red
- Greyscale: 2
- full refresh time: 20s
- Refresh power: 26.4mW(typ.)
- Standby current: <0.01uA(almost 0)
- Viewing Angle: >170°
SPI Timing
Note: Different from the traditional SPI protocol, the data line from the slave to the master is hidden since the device only has a display requirement.
- CS is slave chip select, when CS is low, the chip is enabled.
- DC is data/command control pin, when DC = 0, write command, when DC = 1, write data.
- SCLK is the SPI communication clock.
- SDIN is the data line from the master to the slave in SPI communication.
SPI communication has data transfer timing, which is combined by CPHA and CPOL.
- CPOL determines the level of the serial synchronous clock at an idle state. When CPOL = 0, the level is Low. However, CPOL has little effect on transmission.
- CPHA determines whether data is collected at the first clock edge or at the second clock edge of the serial synchronous clock; when CPHL = 0, data is collected at the first clock edge.
- There are 4 SPI communication modes. SPI0 is commonly used, in which CPHL = 0, CPOL = 0.
As you can see from the figure above, data transmission starts at the first falling edge of SCLK, and 8 bits of data are transferred in one clock cycle. Here, SPI0 is in used, and data is transferred by bits, MSB first.