Difference between revisions of "Template:Pico OLED 1.3 Spec"
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==Pinout== | ==Pinout== | ||
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==OLED and its controller== | ==OLED and its controller== | ||
This OLED integrates the SH1107 controller which has 128x128 bits SRAM, supports 128x128 resolution. The controller features SPI/IIC/ 6800/8080 interface and 256 brightness levels. The resolution of this 1.3inch OLED is only 64x128, only half of the SRAM is used.<br /> | This OLED integrates the SH1107 controller which has 128x128 bits SRAM, supports 128x128 resolution. The controller features SPI/IIC/ 6800/8080 interface and 256 brightness levels. The resolution of this 1.3inch OLED is only 64x128, only half of the SRAM is used.<br /> |
Revision as of 07:01, 10 April 2021
Overview
This 1.3inch OLED display module is designed for Raspberry Pi Pico, 64x128 pixels, support PSI/I2C interface.
Features
- Adopts both 4-wire SPI and I2C interface, better compatibility, fast data rate
- 2x user buttons for easy interacting
- Standard Raspberry Pi Pico header, supports Raspberry Pi Pico series boards
Specification
Working voltage | 2.6V ~ 5.5V |
Current | 40mA |
Controller | SH1107 |
Interface | 4-wire SPI / I2C |
Resolution | 64 x 128 Pixels |
Pixel size | 0.15 × 0.15mm |
Display area | 14.70 × 29.42mm |
Outline dimension | 52.00 x25.00(mm) |
Pinout
OLED and its controller
This OLED integrates the SH1107 controller which has 128x128 bits SRAM, supports 128x128 resolution. The controller features SPI/IIC/ 6800/8080 interface and 256 brightness levels. The resolution of this 1.3inch OLED is only 64x128, only half of the SRAM is used.
This OLED uses four-line SPI and I2C interface for communicating, which supports higher compatibility and speed.
Protocol
Note: The MISO pin is hidden, for more details, you can refer to Datasheet Page11.
CS: Chip selection of the slaver, the chip is activated when CS is Low;
SI(D1): This is MOSI pin, the pin is used to transmit data from master to slaver;
SCL(D0)is the SPI clock
A0: This is the DC pin, it is used to determine the data input, DC=0: command is sent;
SPI communication has data transfer timing, which is combined by CPHA and CPOL.
CPOL determines the level of the serial synchronous clock at an idle state. When CPOL = 0, the level is Low. However, CPOL has little effect on the transmission.
CPHA determines whether data is collected at the first clock edge or at the second clock edge of the serial synchronous clock; when CPHL = 0, data is collected at the first clock edge.
According to the figure, SCL is high in idle and it starts to transmit data at the second edge. therefore the timing is Mode 3 (0x11). Data is transmitted in MSB format.