Template:Pico LCD 2 Spec

Overview

This 2inch LCD display module is designed for Raspberry Pi Pico, embedded ST7789VW driver, 65K RGB colors, 320 x 240 Pixels. SPI interface.

Features

• 320 × 240 resolution, IPS screen, 65K RGB colors, clear and colorful displaying effect.
• SPI interface requires minimal IO pins.
• 4 x user buttons for easy interaction.

Specifications

Parameter name	Parameters
Supply Voltage	2.6V ~ 5.5V
Working current	40mA
Screen Type	IPS
Control Chip	ST7789V
Communication interface	4-wire SPI
Resolution	240(V)RGB x 320(H) Pixels
Pixel size	0.0975(H) x 0.0975(V)mm
Display size	30.6(H) x 40.8(V)mm
Product size	35(H) x 52.00(V) mm

Pinout

LCD & Controller

The built-in controller used in this LCD is ST7789VW, which is an LCD controller with 240 x RGB x 320 pixels, while the pixels of this LCD itself are 240(H)RGB x 320(V), and the internal RAMYIJ of the LCD has been fully used.
The LCD supports 12-bit, 16-bit and 18-bit input color formats per pixel, namely RGB444, RGB565, and RGB666 three color formats, this routine uses RGB565 color format, which is also a commonly used RGB format.
The LCD uses a four-wire SPI communication interface, which can greatly save the GPIO port, and the communication speed will be faster.

Working Protocol

Note: Different from the traditional SPI protocol, the data line from the slave to the master is hidden since the device only has a display requirement.
RESX Is the reset pin, it should be low when powering the module and be higher at other times;；
CSX is slave chip select, when CS is low, the chip is enabled.
D/CX is data/command control pin, when DC = 0, write command, when DC = 1, write data
SDA is the data pin for transmitting RGB data, it works as the MOSI pin of SPI interface;
SCL work s the SCLK pins of SPI interface.
SPI communication has data transfer timing, which is combined by CPHA and CPOL.
CPOL determines the level of the serial synchronous clock at an idle state. When CPOL = 0, the level is Low. However, CPOL has little effect on the transmission.
CPHA determines whether data is collected at the first clock edge or at the second clock edge of the serial synchronous clock; when CPHL = 0, data is collected at the first clock edge.
There are 4 SPI communication modes. SPI0 is commonly used, in which CPHL = 0, CPOL = 0.