Difference between revisions of "CoreEP4CE6"
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*[[OpenEP4CE6-C User Manual|User Manual]] | *[[OpenEP4CE6-C User Manual|User Manual]] | ||
*[[:File:CoreEP4CE6-Schematic.pdf|Schematic]] | *[[:File:CoreEP4CE6-Schematic.pdf|Schematic]] | ||
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*Demo Code: [[:File:EP4CE6-Verilog-VHDL.7z|Verilog | VHDL]] | [[:File:EP4CE6-NIOS.7z|NIOS]] | *Demo Code: [[:File:EP4CE6-Verilog-VHDL.7z|Verilog | VHDL]] | [[:File:EP4CE6-NIOS.7z|NIOS]] | ||
*[[:File: EP4CE6-pin-conf.txt |Pin Configuration ]] | *[[:File: EP4CE6-pin-conf.txt |Pin Configuration ]] | ||
Revision as of 11:20, 25 June 2021
[中文]
Introduction
FPGA core board, features the ALTERA Cyclone IV chip EP4CE6E22C8N onboard
| More |
Resources
- User Manual
- Schematic
- Demo Code: Verilog | VHDL | NIOS
- Pin Configuration
- Software
- Datasheets
FAQ
Support
Support
If you require technical support, please go to the Support page and open a ticket.