Difference between revisions of "CoreEP3C16"
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==Resources== | ==Resources== | ||
*[[:File:CoreEP3C16-Schematic.pdf|Schematic]] | *[[:File:CoreEP3C16-Schematic.pdf|Schematic]] | ||
| + | *[[:File:CoreEP3C16-PCB.7z|PCB Layer]] | ||
*Demo Code: [[:File:EP3C16-Verilog-VHDL.7z|Verilog | VHDL]] | [[:File:EP3C16-NIOS.7z|NIOS]] | *Demo Code: [[:File:EP3C16-Verilog-VHDL.7z|Verilog | VHDL]] | [[:File:EP3C16-NIOS.7z|NIOS]] | ||
<!--*[[:File:EP3C16-Demo-Code-User-Guide.xls|User Manual]]--> | <!--*[[:File:EP3C16-Demo-Code-User-Guide.xls|User Manual]]--> | ||
Revision as of 07:50, 21 March 2017
[中文]
Introduction
FPGA core board, features the ALTERA Cyclone III chip EP3C16Q240C8N onboard
| More |
Resources
- Schematic
- PCB Layer
- Demo Code: Verilog | VHDL | NIOS
- User Manual
- Pin Configuration
- Software
- Datasheets
FAQ
Support
Support
If you require technical support, please go to the Support page and open a ticket.