Difference between revisions of "CoreEP2C5"

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==Resources==
 
==Resources==
 
*[[:File:CoreEP2C5-Schematic.pdf|Schematic]]
 
*[[:File:CoreEP2C5-Schematic.pdf|Schematic]]
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*[[:File:CoreEP2C5-PCB.7z|PCB Layer]]
 
*Demo Code: [[:File:EP2C5-Verilog-VHDL.7z|Verilog | VHDL]] | [[:File:EP2C5-NIOS.7z|NIOS]]
 
*Demo Code: [[:File:EP2C5-Verilog-VHDL.7z|Verilog | VHDL]] | [[:File:EP2C5-NIOS.7z|NIOS]]
 
<!--*[[:File:EP2C5-Demo-Code-User-Guide.xls|User Manual]]-->
 
<!--*[[:File:EP2C5-Demo-Code-User-Guide.xls|User Manual]]-->

Revision as of 07:52, 21 March 2017

[中文]

CoreEP2C5
CoreEP2C5

Introduction

FPGA core board, features the ALTERA Cyclone II chip EP2C5T144C8N onboard

More

Resources

FAQ

Support

Support

If you require technical support, please go to the Support page and open a ticket.